1. Field of the Invention
The invention relates generally to metal-semiconductor alloy layers within microelectronic structures. More particularly, the invention relates to buried metal-semiconductor alloy layers within microelectronic structures.
2. Description of the Related Art
Microelectronic structures, including in particular semiconductor structures, are typically fabricated using active devices and passive devices including transistors, diodes, resistors and capacitors. The foregoing active devices and passive devices are typically connected and interconnected using patterned conductor layers that are separated by dielectric layers.
As semiconductor technology has advanced, bulk resistances and surface resistances of patterned conductor layers continue to contribute increasingly proportional quantities of patterned conductor layer resistance based time delays within microelectronic circuits, including in particular semiconductor circuits. Since these patterned conductor layer resistance based time delays may under certain circumstances have a tendency to become greater as semiconductor device based time delays become smaller or remain constant, it becomes increasingly important within advanced semiconductor structure fabrication and semiconductor device fabrication to minimize patterned conductor layer resistance based time delays so that improvements in operational speed of semiconductor devices is not compromised.
In an effort in-part to provide reductions in patterned conductor layer resistance based time delays within semiconductor circuits, the use of metal-semiconductor alloy conductor materials and metal-semiconductor alloy contact materials has evolved.
“Metal-semiconductor alloy conductor materials” and “metal-semiconductor alloy contact materials” are intended as metal-semiconductor compounds that in general have a higher conductivity, (i.e., a lower resistivity) than a base semiconductor material from which they may be comprised. Metal-semiconductor alloys of several metals are known. Metal-semiconductor alloys of transition metals are particularly common.
Various aspects and characteristics of metal-semiconductor alloy layers are known in the semiconductor fabrication art.
For example, Seger et al., in “Lateral encroachment of Ni-silicide in the source/drain regions of ultra-thin silicon-on-insulator,” Appl. Phys. Lett., 86, 53507-1-9 (2005) teaches differential lateral encroachment of a nickel silicide layer located and formed upon a source/drain region of a field effect transistor as a result of thickness of a nickel layer that is used for fabricating the nickel silicide layer while using a self-aligned silicide (i.e., salicide) method.
In addition, Cheng et al., in U.S. Pat. No. 6,737,710 and U.S. Pub. No. 2002/0060346 teaches a field effect transistor structure including a source/drain region having a dual silicide layer. The dual silicide layer includes a first silicide layer located upon an extension region of the source/drain region and a second silicide layer located upon a contact region of the source/drain region.
Further Jawarani, in U.S. Pub. No. 2005/0202664, teaches a method for fabricating a field effect transistor with inhibited lateral encroachment of a silicide layer upon an electrode region (i.e., source/drain electrode region or gate electrode) thereof. The method includes performing a low temperature silicidation anneal (and unreacted metal etch) prior to an encroachment inhibiting ion implant that is followed by higher temperature silicidation anneal.
Still further, Kammler et al. in U.S. Pub No. 2005/0070082 and World Patent No. WO 2005034225 also teaches a field effect transistor device with a dual silicided source/drain region. The dual silicided source/drain region includes: (1) a buried nickel silicide alloy layer that has superior properties with respect to a silicon interface; and (2) a surface cobalt silicide layer located upon the buried nickel silicide layer and having superior contact resistance properties.
Finally, Chen et al., in U.S. Pub. No. 2005/0208762 teaches a method for fabricating a silicide electrode within a semiconductor device with reduced defects. The method uses a halogen doping of a silicide forming metal from which is formed the silicide electrode, prior to annealing the silicide forming metal with a silicon substrate to form the silicide electrode.
Due to their desirable electrical properties within the context of both reduced bulk resistances and reduced contact resistances, metal-semiconductor alloy layers, such as in particular silicide layers, are likely to be of considerable continued importance when fabricating semiconductor devices and semiconductor structures. Thus, desirable within the semiconductor fabrication art are silicide layers having desirable properties, and methods for fabricating those silicide layers.